Changes in input/output (I/O) timing can severely impact I/O performance, particularly with respect to high performance or high frequency I/O design. Some high speed computers rely on synchronous interfaces between various integrated circuits and subsystems that make up the computer. In order to ensure synchronicity a common clock signal is typically propagated to each of the synchronous components of the computer system.
Any skew introduced into the clock signal during propagation can have a significant impact on performance. Although shifting integer multiples of a clock cycle may be permissible (so that the clock edges are aligned), any other amount of shifting of the clock signal can create uncertainty as to validity. For example, data defined to be valid during a particular portion of a master clock cycle may not be valid at the same portion of a propagated clock signal if the propagated clock signal is skewed with respect to the master clock signal or another propagated clock signal. The performance impact can range from introducing undesirable input/output wait delays to rendering the computer system inoperable.
Typically the clock signal is propagated to multiple components using circuit board traces. The amount of skew in the propagated signal is proportional to the electrical length of the trace. Consider the propagation of a clock signal to two integrated circuits. One method of ensuring propagation of a clock signal so that the two integrated circuits are operating synchronously to each other is to ensure that the electrical length of the traces to each integrated circuit from a common clock signal are identical.
Ensuring accurate clock signal propagation can create difficulty in designing the physical layout of a computer system having multiple integrated circuits and subsystems. As the number of integrated circuits and subsystems increases, the design process becomes significantly more complicated.
Another disadvantage of this technique is that it is not particularly applicable to scaleable systems. Consider a system having hierarchies of synchronous subsystems. In order to ensure relative synchronicity, each subsystem should be designed so that the electrical lengths of the traces between the common clock signal and each component within the subsystem is the same. Moreover, each of the subsystems would need to be designed so that the electrical length from the common clock signal to a component in one subsystem is the same as the electrical length from the common clock signal to a component in another subsystem. The process becomes even more complicated with multiple hierarchies of subsystems or components.